In the formation of integrated circuits, standard cells are often used as base elements for building integrated circuits. The standard cells are placed and routed to form functional circuits. In typical layouts of standard cells, power rails are laid out on the boundaries of the cells. When a plurality of standard cells are placed as rows, the power rails of the standard cells in the same row are connected with each other to form a long power rail that may expand through, for example, thousands or more standard cells. The power rails in neighboring rows are merged to form a power rail having a width twice as wide as the power rail in a stand-alone standard cell. For example, the VDD power rail of a row is merged with another VDD power rail of a neighboring row, and the VSS power rail of a row is merged with another VSS power rail of a neighboring row. Accordingly, with a circuit including a plurality of rows, the VDD power rails and VSS power rails are placed in an alternating pattern.
To provide power to the standard cells, additional metal features are needed to connect the power rails to the features in the standard cells. For example, to connect a VDD power rail to a source of a PMOS transistor in a standard cell (such as an inverter cell), a metal feature (known as a jog) is formed in the same metal layer as the VDD power rail. The jog has one end connected to the VDD power rail. The jog extends to directly over the source of the PMOS transistors, so that a contact plug may be formed to connect the jog to the source of the PMOS transistor.
When the standard cells are placed as rows, there are many jogs extending from a power rail to directly over the respective standard cells. Since power rails are quite wide compared to jogs, there are process issues to be solved for forming the jogs. In addition, existing power routing schemes require significant amounts of routing resource (such as chip area) that otherwise could be used for routing signal lines.